The present invention relates to a semiconductor device and to a technique for the manufacture thereof. More particularly, it relates to a technique that is applicable to a semiconductor device having a nonvolatile memory, such as an EEPROM (Electrically Erasable Programmable Read Only Memory) or a flash memory, or a method of manufacturing the same.
A nonvolatile memory cell that was studied by the present inventors has, other than a floating gate electrode and a control gate electrode, a third gate electrode, which is referred to as an assist gate electrode. Over the principal surface of a semiconductor substrate, a plurality of assist gate electrodes, each in the form of a band, as seen in plan configuration, are arranged in such a manner as to abut one another. In an insulating film covering the plurality of assist gate electrodes, trenches are formed between each of the adjacent assist gate electrodes, and a floating gate electrode, which is convex as seen in cross section, is provided on the side and bottom of each trench. Over the floating gate electrode, a control gate electrode is provided via an interlayer film.
Incidentally, for example, Japanese Unexamined Patent Publication No. 2000-188346, discloses an NAND type flash memory cell configured such that, between adjacent STI regions for isolation formed over the principal surface of a semiconductor substrate, a floating gate electrode, which is convex as seen in cross section, is provided, and a control gate electrode is provided via an interlayer film in such a manner as to cover the surface. (Patent Document 1).
[Patent Document 1] Japanese Unexamined Patent Publication No. 2000-188346